| 术语 | JK flip-flop |
| 释义 | JK flip-flop JK触发器;［JK正反器］ A flip-flop having two inputs designated J and K. At the application of a clock pulse, a “1” on the J input and a “0” on the K input will set the flip -flop to the “1” state. A “1” on the K input and a “0” on the J input will reset it to the “0” state. Placing “1's” simultaneously on both inputs will cause it to change state regardless of the previous state. Inputs of J=0 and K=0 will prevent any change. 一种触发器,具有指定的两个输入端J和K。当施加一个时钟脉冲时,若J输入为“1”, K输入为“0”,则触发器被置为“1”；若K输入为“1”,J输入为“0”,则触发器被重新置 为“0”;若K与J输入同时为1时,触发器状态翻转。而当K与J输入均为“0”时,则状态不变。 参阅flip-flop。 |
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