| 术语 | master/slave flip-flop |
| 释义 | master/slave flip-flop 主从触发器;［主从正反器］ A modern integrated-circuit flip-flop designed for high noise immunity. It is an advanced version of the versatile JK flip-flop, configured with two half-shift registers connected in tandem. The input half is the master, the output half the slave. A master-slave unit works on both edgesof the activating clock pulse. The information is loaded into the master on the leading edge, without effecting the outputs of the slave. When the data has stabilized, the trailing edge comes along to transfer it to the outputs of the slave. It is also known as a dual-rank JK flip-flop. 一种现代的高抗噪 声集成电路触发器,是通用JK触发器的改进型,由二只半移位寄存器级连而成。输入半部 为主触发器,输出半部为从触发器,主从触发器由时钟脉冲前后沿触发而工作。信息在 脉冲前沿时进入主触发器而不影响从触发器的输出;当数据已稳定时,脉冲后沿到来, 使其转移至从触发器。也称为双级JK触发器。 |
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