| 术语 | bus cycles |
| 释义 | bus cycles 总线周期;［汇流排周期］ The change cycles of the bus circuits states. The typical bus cycles (with respect to the processor) are: Data word transfer in: equivalent to read operation, Data word transfer in, followed by word transfer out: equivalent to Read／Modify Write: Data word transfer in followed by byte transfer out: equivalent to Read／Modify Write: Data word transfer out: equivalent to write operation; Data byte transfer out: equivalent to write operation. 在进行各种操作时,总线电路状态的变化周期。典型的总线周期(相对处理机而言)有: 数据字传入,相当于读操作;数据字传入,随后传出,相当于读入、修改后写;修改后写;数据 字传入,随后按字节传出,也相当于读入、修改后写;数据字传出,相当于写操作;数据字节传 出,也相当于写操作。 |
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