计算机术语“gatelevel simulation”的中英文意思、释义、翻译及用法-计算机英汉双解词典

术语	gatelevel simulation
释义	gatelevel simulation 门级模拟;［闸级模拟］ A detailed level of logic simulation that includes timing analyses (both minimum and maximum rise/fall propagation delays) and race analyses (dynamic design rule checking) as well as provision for undefined and high impedance states. 一种精细的逻辑模拟,它包括定时分析(最大及最小上升/下降传输延时)和竞争分析 (动态设计法则检验),也考虑了不确定的和高阻状态的情况。
随便看	VECTRAN Veich diagram Venn diagram verb vergepunched card verification verification mode verification setting verification test verifier verify verifying unit Vernam cipher version version number verso vertical blanking interval vertical check vertical constraints graph vertical feed vertical format vertical formatting vertical format unit (VFU) vertical justification vertically displayed records

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